The present invention relates to a non-volatile memory circuit constituted by cell transistors which have a non-conductive trapping gate and which are capable of storing multiple bit data, and, more particularly, to a non-volatile memory circuit which has a cell array constitution capable of simultaneously reading out stored data from a multiplicity of cell transistors.
Non-volatile memories that utilize semiconductors are widely used as information recording media because such non-volatile memories are capable of holding information even if the power supply is OFF, and of high speed read-out. In recent years, non-volatile memories have been utilized in mobile information terminals, and utilized as recording media for digital cameras and for digital music in the form of MP3 data, for example.
Non-volatile memories, such as the flash memories that are currently in widespread use, are constructed having, on a channel region between a source region and drain region, a conductive floating gate and a control gate. A non-volatile memory of this kind is constituted such that a floating gate is buried in a gate insulating film, and one-bit information is stored according to whether charge is or is not injected into this floating gate. Due to the fact that the floating gate of such widely used non-volatile memories is conductive, when defects, however small, are present in the gate oxide film, electrons in the floating gate are all lost via these defects and there is a problem in that high reliability is unattainable.
Other than the widely used non-volatile memories mentioned above, a new type of non-volatile memory has been proposed that is provided with a non-conductive charge trapping gate in place of a floating gate, and that stores two-bit information by causing charge to be trapped locally at the source side and the drain side of the trapping gate. For example, a non-volatile memory of this kind is disclosed in the PCT application WO99/07000 xe2x80x9cTwo Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d. Since the trapping gate of this non-volatile memory is non-conductive, the probability of electrons injected locally being lost is low, and it is thus possible to make reliability high.
FIG. 1 is a figure to show the constitution of a cell transistor of the above-mentioned conventional two-bit non-volatile memory. (1) of FIG. 1 is a cross-sectional view thereof, and (2) of FIG. 1 is an equivalent circuit diagram thereof. Source-drain regions SD1, SD2 are formed at the surface of a silicon substrate 1, and a trapping gate TG formed from a silicon nitride film or the like, and a control gate CG of a conductive material, are formed on a channel region. The trapping gate TG is buried in an insulating film 2 made of silicon oxide film or the like such that the whole body is a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure. By utilizing the difference in the bandgaps of the silicon nitride film and the silicon oxide film, it is possible to cause charge to be trapped and held in the silicon nitride film.
One feature of the non-volatile memory is that the trapping gate TG is constituted from a non-conductive substance such as an insulating body, or a dielectric body, and, in a case in which charge is injected into this trapping gate TG, charge within the trapping gate is unable to move. As a result, it is possible to make a distinction between a case in which charge is injected in the vicinity of a first source-drain region SD1, and a case in which charge is injected in the vicinity of a second source-drain region SD2, and it is thus possible to record two-bit data.
(2) of FIG. 1 is an equivalent circuit diagram of the above-mentioned two-bit non-volatile memory. Since the trapping gate TG is non-conductive, this trapping gate TG is equivalent to a constitution in which separate MOS transistors are respectively formed in a first trapping gate region TSD1 in the vicinity of the first source-drain region SD1, and in a second trapping gate region TSD2 in the vicinity of the second source-drain region SD2. Further, in the course of the above-described read-out and programming (write) operations, the first and second source-drain regions SD1, SD2 are utilized either as source regions or drain regions, and these source or drain regions SD1, SD2 are therefore referred to, in this specification, as the first source-drain region SD1 and the second source-drain region SD2, respectively.
FIG. 2 is a figure to illustrate programming, erasure and read-out of a conventional two-bit non-volatile memory. The voltage applied to the first source-drain region SD1 is termed V(SD1), the voltage applied to the second source-drain region SD2 is termed V(SD2), and the voltage applied to the control gate CG is termed Vg.
As shown in (1) of FIG. 2, the programming (write) of the non-volatile storage memory is executed by applying voltages Vg=10V, V(SD1)=0V, V(SD2)=6V, for example, and by thus injecting hot electrons produced in the vicinity of the second source-drain region SD2 into the second trapping gate region TSD2 close to the second source-drain region SD2.
In addition, in the course of an erase operation, as shown in (2) FIG. 2, Vg=xe2x88x925V is applied to the control gate CG, and 5V is applied to the first or second source-drain region SD1 or SD2, or to both of them, to extract electrons from the trapping gate TG by utilizing the FN tunnel effect (the Fowler-Nordheim Tunnel effect). As a result of injection, at the same time, of hot holes produced in the vicinity of the source-drain regions SD1, SD2, into the trapping gate TG, the charge is neutralized within the trapping gate TG.
Next, with regard to read-out, a voltage, whose bias is the reverse of the voltage of the programming operation, is applied between the first and second source-drain regions SD1, SD2, to detect whether or not electrons are trapped in the second trapping gate region TSD2. In other words, in order to read out the state of the second trapping gate region TSD2, voltages applied are Vg=3V, V(SD1)=1.6V, V(SD2)=0V, for example. Here, as shown in (3) of FIG. 2, when electrons are present in the second trapping gate region TSD2 in the vicinity of the second source-drain region SD2, the channel below the gate does not extend so as to touch the second source-drain region SD2, and, consequently, a channel current does not flow (0 data storage state). Conversely, as shown in (4) of FIG. 2, when electrons are not present in the second trapping gate region TSD2 in the vicinity of the second source-drain region SD2, the channel reaches as far as the second source-drain region SD2, and, consequently, a channel current flows (1 data storage state). It is thus possible to detect whether or not electrons have accumulated in the second trapping gate region TSD2, and to detect the ON and OFF of a cell transistor, that is, the existence of a current.
Furthermore, in read-out of the non-volatile storage memory, when, as shown in (5) of FIG. 2, voltages applied are: Vg=3V, V(SD1)=0V, V(SD2)=1.6V, i.e. when the voltage application state between the first and second source-drain regions is the reverse of that in (3) of FIG. 2 mentioned above, even if electrons are, for example, present in the second trapping gate region TSD2, the state is the same as a MOS transistor whose channel is pinched off, and, as a result of an expanding depletion layer between the second source-drain region and the substrate, a channel current flows. Therefore, in a voltage application state of this kind, it is possible to detect whether or not electrons have accumulated in the first trapping gate region TSD1 in the vicinity of the first source-drain region SD1, irrespective of the existence of electrons in the second trapping gate region TSD2.
As described above, a conventional memory is capable of recording two-bit information by means of the accumulation or non-accumulation of electrons in the nitride film region TSD1 in the vicinity of the first source-drain region SD1 and in the nitride film region TSD2 in the vicinity of the second source-drain region SD2, and is therefore advantageous with respect to a larger capacity and a cost reduction per chip as a result of a reduced chip surface area.
FIG. 3 is a figure to show a state in which two-bit information is recorded in the above-mentioned non-volatile memory. In the figure, black spots represent electrons. (1) of FIG. 3 shows a state data=11 in which electrons are not captured in either of the first or second trapping gate regions TSD1, TSD2. (2) of FIG. 3 shows a state data=01 in which electrons are captured in the second trapping gate region TSD2. (3) of FIG. 3 shows a state data=00 in which electrons are captured in the first and second trapping gate regions TSD1, TSD2. Further, (4) of FIG. 3 shows a state data=10 in which electrons are captured in the first trapping gate region TSD1.
FIG. 4 is a figure to show the constitution of a conventional memory cell array. As described hereinabove, a non-volatile memory with a two-bit recording capability applies voltages from one source-drain region of a cell transistor to the other source-drain region thereof to perform a desired data read-out. Therefore, such a non-volatile memory is capable of applying voltages in both directions to the same cell transistor, and there is thus a requirement to perform the read-out of data from each of two source-drain lines SDL that are connected with a source-drain region on both sides.
According to the conventional example shown in FIG. 4, four word lines WL0 to WL3, and cell transistors M1 to M8 whose control gates are each connected with these word lines, are provided. Further, for a large capacity, the source-drain regions of adjacent cell transistors are shared and common source-drain lines SDL0 to SDL7 are connected. In addition, for every four cell transistors, one pair of column lines L1, L2 and L3, L4, and four selective transistors Q1 to Q4 of one set, which connect these column lines and source-drain lines SDL0 to SDL7, are provided. In response to select signals SEL1 to SEL4, any of selective transistors Q1 to Q4 are conductive such that column lines L1 to L4 are suitably connected with source-drain lines.
FIG. 5 is a chart to illustrate the operation of FIG. 4. When cell transistor M1 is selected, as shown in FIG. 5, select signals SEL1 and SEL3 are at an L level such that transistors Q1, Q3 are non-conductive, and select signals SEL2, SEL4 are at an H level such that transistors Q2, Q4 are conductive. As a result, the source-drain lines SDL0, SDL1 of the cell transistor M1 are respectively connected with the column lines L1, L2. Therefore, when 0V is applied to column line L2 and a predetermined read-out voltage (1.6V) is applied for a bit line to column line L1, a voltage is applied to cell transistor M1 from the left side to the right side thereof, and it is possible to detect whether or not a current is flowing in column line L1 by means of a sense amp circuit (not shown).
At this time, the source-drain lines SDL4, SDL5 of the cell transistor M5 are also respectively connected with column lines L3, L4. Moreover, through selection of the word line WL0, while the simultaneously selected cell transistors M2, M3, M4 are conductive or produce a leak current, there is a possibility that read-out of the cell transistor M1 cannot be adequately performed. Consequently, in order to prevent such a possibility, column lines L3, L4 both assume a floating state.
Therefore, data which is read out through selection of word line WL0 is only one stored data of cell transistor M1. When, with the select signals in an unchanged condition, 0V is applied to column line L1 and a predetermined voltage (1.6V) is applied to column line L2, it is possible to read out another stored data of cell transistor M1. In any case, actuation of select signals SEL1 to SEL4 only permits two-bit data of a single cell transistor to be read-out.
Of the four associated cell transistors, the read-out of the remaining cell transistors M2, M3, M4 is the same, as shown in FIG. 5. In this case also, in response to selection of word line WL0, stored data of the cell transistors is read out one by one.
Since, in comparison with a widely used flash memory, a two-bit non-volatile memory having a non-conductive trapping gate is capable of storing two-bit data, same is preferable as a large capacity memory. On the other hand, since, in the read-out operation thereof, according to the data which is to be read out, the direction of the voltage applied to the source-drain regions is reversed, as shown in FIGS. 4, 5, there are problems in that the read-out circuit is complex and the read-out throughput is poor.
Therefore, an object of the present invention is to provide a multiple bit non-volatile memory circuit in which the read-out throughput is high.
A further object of the present invention is to provide a multiple bit non-volatile memory circuit, which, by means of the selection of one word line, is capable of simultaneously reading out stored data of a plurality of cell transistors.
A further object of the present invention is to provide a multiple bit non-volatile memory circuit which has a cell array structure capable of high speed read-out.
In order to resolve the above-mentioned objects, one aspect of the present invention is a non-volatile memory circuit in which a plurality of cell transistors having a non-conductive trapping gate are arranged, comprising: a plurality of source-drain lines, which are connected commonly with the source-drain regions of cell transistors adjacent in row direction, wherein these adjacent source-drain lines are set to a floating state, a read-out voltage application state, a reference voltage state, a read-out voltage state, and a floating state, and the source-drain lines in the read-out voltage state is caused to function as bit lines, such that a plurality of data are read out simultaneously.
According to a preferred embodiment of the present invention, by causing a group of source-drain lines of the above five states to be sequentially shifted or moved, it is possible to read-out, at high-speed, multiple bit data which has been recorded in cell transistors, and to therefore improve the read-out throughput.
In order to resolve the above-mentioned objects, another aspect of the present invention is a non-volatile memory circuit for recording multiple bit information comprising: a plurality of cell transistors, which have first and second source-drain regions formed at a substrate surface, and a first insulating layer, a non-conductive trapping gate, a second insulating layer, and a control gate, formed sequentially on a channel region between the first and second source-drain regions, wherein cell transistors record data by trapping charge locally at at least both ends of the trapping gate; a plurality of word lines, which are connected with the respective control gate of the plurality of cell transistors arranged in a row direction; a plurality of source-drain lines, which are connected commonly with the source-drain regions of the cell transistors that are adjacent in the row direction; and a plurality of page buffers, which are respectively connected with the plurality of source-drain lines, which supply, to each source-drain line within a group of adjacent source-drain lines, a combination of a floating state, a read-out voltage state, a reference voltage state, a read-out voltage state, and a floating state, in sequential order, and which read out the recorded data from the source-drain lines in the read-out voltage state.
Further, according to the preferred embodiment of the above invention, the plurality of page buffers shift, in a predetermined sequential order, the group of adjacent source-drain lines to which the combination of states is supplied.
In this manner, it is possible to suitably read out all the multiple bit data of the cell transistors.
Further, according to the preferred embodiment of the above invention, the plurality of page buffers output the read-out recorded data each time the combination of states is supplied to a first group of adjacent source-drain lines which has, at both ends thereof, the source-drain lines of an odd number, and to a second group of adjacent source-drain lines which has, at both ends thereof, the source-drain lines of an even number.
By supplying the above combination of states to the first group of adjacent source-drain lines and to the second group of adjacent source-drain lines, recorded data in a group of eight adjacent cell transistors, for example, can be read out in eight bits to page buffers. At this stage, it is preferable that data in page buffers should be suitably outputted.